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18-bit, 1.33 msps pulsar 10.5 mw adc in msop/lfcsp data sheet ad7984 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2007C2014 analog devices, inc. all rights reserved. technical support www.analog.com features 18-bit resolution with no missing codes throughput: 1.33 msps low power dissipation: 10.5 mw at 1.33 msps inl: 2.25 lsb maximum dynamic range: 99.7 db typical true differential analog input range: v ref 0 v to v ref with v ref between 2.9 v to 5.0 v allows use of any input range easy to drive with the ada4941 no pipeline delay single-supply 2.5 v operation wi th 1.8 v/2.5 v/3 v/5 v logic interface proprietary serial interface spi/qspi/microwire?/dsp compatible ability to daisy-chain multiple adcs and busy indicator 10-lead msop (msop-8 size) and 10-lead 3 mm 3 mm lfcsp, sot-23 size applications battery-powered equipment data acquisition systems medical instruments seismic data acquisition systems application diagram figure 1. general description the ad7984 1 is an 18-bit, successive approximation, analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 18-bit sampling adc and a versatile serial interface port. on the cnv rising edge, the ad7984 samples the voltage difference between the in+ and in? pins. the voltages on these pins usually swing in opposite phases between 0 v and v ref . the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad7984 is available in a 10-lead msop or a 10-lead lfcsp with operation specified from ?40c to +85c. 1 protected by u.s. patent 6,703,961. table 1. msop, lfcsp 14-/16-/18-bit pulsar? adc type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 14-bit ad7940 ad7942 1 ad7946 1 16-bit ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941-x ad7683 ad7687 1 ad7688 1 ad7983 1 ada4841-x ad7684 ad7694 ad7693 1 ad7988-1 ad7988-5 18-bit ad7989-1 ad7691 1 ad7690 1 ad7982 1 ada4941-x ad7989-5 ad7984 1 ada4841-x 1 pin-for-pin compatible. ad7984 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to 5v ada4941 3- or 4-wire interface (spi, cs daisy chain) 2.9v to 5v 2.5v 10v, 5v, .. 0 6973-001
ad7984* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7984 evaluation kit ? precision adc pmod compatible boards documentation application notes ? an-742: frequency domain response of switched- capacitor adcs ? an-931: understanding pulsar adc support circuitry ? an-932: power supply sequencing data sheet ? ad7984: 18-bit, 1.33 msps pulsar 10.5 mw adc in msop/ lfcsp data sheet technical books ? the data conversion handbook, 2005 user guides ? ug-340: evaluation board for the 10-lead family 14-/16-/ 18-bit pulsar adcs ? ug-682: 6-lead sot-23 adc driver for the 8-/10-lead family of 14-/16-/18-bit pulsar adc evaluation boards software and systems requirements ? ad7984 fmc-sdp interposer & evaluation board / xilinx kc705 reference design ? bemicro fpga project for ad7984 with nios driver tools and simulations ? ad7984 ibis model reference designs ? cn0033 ? cn0269 reference materials product selection guide ? sar adc & driver quick-match guide technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc tutorials ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" ? mt-074: differential drivers for precision adcs design resources ? ad7984 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7984 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7984 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram ........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical p erformance characteristics ............................................. 8 terminology .................................................................................... 11 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converter operation .................................................................. 12 typic al connection diagram .................................................... 13 analog inputs .............................................................................. 14 driver amplifier choice ........................................................... 14 single - to - differential driver .................................................... 15 voltage reference input ............................................................ 15 power supply ............................................................................... 15 digital interface .......................................................................... 16 cs mode, 3 - wire without busy indicator ............................. 17 cs mode, 3 - wire with busy indicator .................................... 18 cs mode, 4 - wire without busy indicator ............................. 19 cs mode, 4 - wire with busy indicator .................................... 20 chain mode without busy indicator ...................................... 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating the ad7984 performance ...................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 7 /14 rev. a to rev. b changed qfn (lfcsp) to lfcsp .............................. throughout changes to features section and table 1 ...................................... 1 added patent n ote , note 1 .............................................................. 1 changes to power supply section ................................................ 15 changes to evaluating the ad 7984 performance section ........ 23 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 8 / 1 0 rev. 0 to rev. a updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 1 1 /07 revision 0: ini tial version rev. b | page 2 of 24
data sheet ad7984 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, ref = 5 v, t a = ? 40c to +85c, unless otherwise noted. table 2 . parameter conditions min typ max unit resolution 18 bits analog input voltage range in+ ? in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common - mode input range in+, in? v ref 0.475 v ref 0.5 v ref 0.525 v analog input cmrr f in = 450 k hz 67 db 1 leakage current at 25c acquisition phase 200 na input impedance see the analog input s section accuracy no missing codes 18 bits differential linearity error ? 1 + 1.5 lsb 2 integral linearity error ?2 .25 +2 .25 lsb 2 transition noise 0.95 lsb 2 gain error, t min to t max 3 ? 0.075 0.022 + 0.075 % of fs gain error temperature drift ? 0.6 ppm/c zero error, t min to t max 3 ? 700 100 + 700 v zero temperature drift 0. 3 ppm/c power supply sensitivity vdd = 2.5 v 5% 90 d b 1 throughput conversion rate 0 1 .33 msps transient response full - scale step 2 9 0 ns ac accuracy dynamic range v ref = 5 v 9 9 .7 db 1 signal - to - noise, snr f in = 1 khz, v ref = 5 v, t a = 25c 96.5 98.5 db 1 spurious - free dynamic range, sfdr f in = 10 khz 112.5 db 1 total harmonic distortion 4 , thd f in = 10 khz ?1 10.5 db 1 signal - to - (noise + distortion), sinad f in = 10 khz, v ref = 5 v, t a = 25c 98 db 1 1 all specifications expressed in decibels are referred to a full - scale input fs r and t ested with an input signal at 0.5 db below full scale, unless otherwise specified. 2 lsb means least significant bit. with the 5 v input range, one lsb is 38.15 v. 3 see terminology section. these specifications include full temperature range variation but not the error contribution from the external refer ence. 4 tested fully in production at f in = 1 khz. rev. b | page 3 of 24
ad7984 data sheet vdd = 2.5 v, vio = 2.3 v to 5.5 v, ref = 5 v, t a = ? 40c to +85c, unless otherwise noted. table 3 . parameter conditions min typ max unit reference voltage range 2. 9 5.1 v load current 1 .33 msps 520 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay 2 ns digital inputs logic levels v il vio > 3 v C 0.3 + 0.3 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v v il vio 3 v C 0.3 + 0.1 vio v v ih vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 18 bits , twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.37 5 2.5 2.6 25 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v 1.1 m a power dissipation 1.33 msps throughput 10.5 14 mw energy per conversion 7.9 nj/sample temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digit al inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact an analog devices, inc., sales representative for the extended temperature range. rev. b | page 4 of 24
data sheet ad7984 timing specification s t a = ?40c to +85c , vdd = 2.37 v to 2.63 v, vio = 2.3 v to 5.5 v, unless otherwise not ed. 1 table 4 . parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 300 500 ns acquisition time t acq 250 ns time between conversions t cyc 750 ns cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck vio above 4.5 v 10 .5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns 1 see figure 2 and figure 3 for load conditions. figure 2 . load circuit for digital interface timing figure 3 . voltage levels for timing 500a i ol 500a i oh 1.4v to sdo c l 20pf 06973-002 x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90, and y = 10; for vio > 3.0v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 06973-003 rev. b | page 5 of 24
ad7984 data sheet absolute maximum rat ings table 5 . parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to +3.0 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 10 - lead msop 200c/w 10 - lead lfcsp 48.7c/w jc thermal impedance 10 - lead msop 44c/w 10 - lead lfcsp 2.96c/w lead temperatures vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog inputs section for an explanation of in+ and in?. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de vice reliability. esd caution rev. b | page 6 of 24
data sheet ad7984 rev. b | page 7 of 24 pin configurations and function descriptions figure 4. 10-lead ms op pin configuration figure 5. 10-lead lfcsp pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is 2.9 v to 5.1 v. this pin is referred to the gnd pin and should be decoupled closely to the gnd pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its rising edge, it initiates the conversions and selects the interface mode of the part: chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is select ed, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple fe atures. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the c nv rising edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cnv rising edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v ). 1 ai = analog input, di = digital input, do = digital output, and p = power. ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7984 top view (not to scale) 06973-004 ref vdd in+ in? gnd vio sdi sck sdo cnv 06973-005 1 2 3 4 10 9 8 7 5 6 *exposed paddle can be connected to ground. ad7984 (exposed pad)*
ad7984 data sheet typical performance characteristics v dd = 2.5 v, ref = 5.0 v, v io = 3.3 v . figure 6 . integral nonlinearity vs. code figure 7 . histogram of a dc input at the code center figure 8 . fft plot figure 9. differential nonlinearity vs. code figure 10 . histogram of a dc input at the code transition figure 11 . snr vs. input level 2.0 ?2.0 0 262144 06973-032 code inl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 65536 131072 196608 positive inl: +1.07lsb negative inl: ?0.73lsb 60k 0 1c 06973-041 code in hex counts 50k 40k 30k 20k 10k 1d 1e 0 0 7 6 0 0 1f 326 20 21 22 23 24 25 326 26 27 28 5992 32350 55354 31003 5708 0 ?180 0 06973-033 frequency (khz) amplitude (db of full scale) ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 100 200 300 400 500 600 f s = 1.33msps f in = 10khz snr = 98.2db thd = ?110.6db sfdr = 112.5db sinad = 98.0db 2.0 ?2.0 0 262144 06973-038 code dnl (lsb) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 65536 131072 196608 positive dnl: +0.63lsb negative dnl: ?0.34lsb 60k 0 1d 06973-042 code in hex counts 50k 40k 30k 20k 10k 1e 1f 0 0 2 20 69 21 22 23 24 25 26 27 37 28 29 0 0 1801 1378 16593 14653 48273 48266 100 90 ?10 0 06973-039 input level (db of full scale) snr (db) 99 98 97 96 95 94 93 92 91 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 rev. b | page 8 of 24
data sheet ad7984 figure 12 . snr, sinad, and enob vs. reference voltage figure 13 . snr vs. temperature figure 14 . sinad vs. frequency figure 15 . thd vs. reference voltage figure 16 . thd vs. temperature figure 17 . thd vs. frequency 100 80 2.5 5.5 reference voltage (v) snr, sinad (db) 95 90 85 18 14 enob (bits) 17 16 15 3.0 3.5 4.0 4.5 5.0 06973-043 enob snr sinad 100 90 ?55 105 06973-044 temperature (c) snr (db) 98 96 94 92 ?35 ?15 5 25 45 65 85 100 80 1000 06973-034 frequency (khz) sinad (db) 1 10 100 95 90 85 ?100 ?120 2.5 5.5 reference voltage (v) thd (db) ?105 ?110 ?115 3.0 3.5 4.0 4.5 5.0 06973-045 ?100 ?120 ?55 125 06973-046 temperature (c) thd (db) ?105 ?110 ?115 ?35 ?15 5 25 45 65 85 105 ?80 ? 1 15 1000 06973-040 frequency (khz) thd (db) 1 10 100 ?85 ?90 ?95 ?100 ?105 ?110 rev. b | page 9 of 24
ad7984 data sheet figure 18 . operating currents vs. supply figure 19 . standby currents vs. temperature figure 20 . operating currents vs. temperature 2.5 0 2.375 2.625 06973-035 v dd voltage (v) operating currents (ma) 2.0 1.5 1.0 0.5 2.425 2.475 2.525 2.575 i vdd i ref i vio 1.5 0.5 ?55 125 06973-036 temperature (c) standby currents (ma) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 ?35 ?15 5 25 45 65 85 105 i vdd + i vio 2.5 0 ?55 125 06973-037 temperature (c) operating currents (ma) ?35 ?15 5 25 45 65 85 105 2.0 1.5 1.0 0.5 i vdd i ref i vio rev. b | page 10 of 24
data sheet ad7984 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale throug h positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 22). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this idea l value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01 ) should occur at a level ? lsb above nominal negative full scale (? 4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11 ) should occur for an analog voltage 1 ? lsb below the nomi nal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious - free dyna mic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise - free code resolution noise - free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise - free code resoluti on = log 2 (2 n / peak - to - peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 dbf so that it includes all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms su m of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure ment of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. rev. b | page 11 of 24
ad7984 data sheet th e ory of operation figure 21 . adc simplified schematic circuit information the ad7984 is a fast, low power, single - supply, precise , 18- bit adc using a successive approximation architecture and is capable of converting 1, 33 0,000 samples per second (1 .33 msps). the ad7984 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7984 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 10 - lead msop or a tiny 10 - lead lfcsp that allows space savings and flexible configurations. it is pin - for - pin - compatible with the 1 8 - bit ad7982 . converter operation the ad7984 is a successive appr oximation adc based on a charge redistribution dac. figure 21 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary - weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the i nput of the comparator are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acqu isition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore , the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref, t he comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4 ... v ref /262 , 144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, th e part returns to the acquisition phase , and the control logic generates the adc output code and a busy signal indicator. because the ad7984 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. c o m p c o n t r o l l o g i c s w i t c h es c o n t r o l b u s y o u t p u t c o d e c n v c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref gnd in? 06973-011 rev. b | page 12 of 24
data sheet ad7984 rev. b | page 13 of 24 transfer functions the ideal transfer characteristic for the ad7984 is shown in figure 22 and table 7. figure 22. adc ideal transfer function table 7. output codes and ideal input voltages description analog input v ref = 5 v digital output code (hex) fsr ? 1 lsb +4.999962 v 0x1ffff 1 midscale + 1 lsb +38.15 v 0x00001 midscale 0 v 0x00000 midscale ? 1 lsb ?38.15 v 0x3ffff ?fsr + 1 lsb ?4.999962 v 0x20001 ?fsr ?5 v 0x20000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection diagram figure 23 shows an example of the recommended connection diagram for the ad7984 when multiple supplies are available. figure 23. typical application diagram with multiple supplies 100 ... 000 100 ... 001 100 ... 010 011 ... 101 011 ... 110 011 ... 111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 0 6973-012 2.7nf 15 ? v? 0 to vref v+ 4 2.7nf 15 ? v? v ref to 0 v+ 4 10f 2 ref 1 ref vdd vio gnd in+ in? sdi sck sdo cnv ad7984 100nf 100nf 3-wire interface 2.5v 1.8v to 5v v+ ada4841 2, 3 notes 1 see voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see recommended layout in figure 40 and figure 41. 3 see driver amplifier choice section. 4 optional filter. see analog inputs section. 06973-013
ad7984 data sheet analog input s figure 24 shows an equivalent circuit of the input structure of the ad7984 . the two diodes , d1 and d2, provide esd protection for the analog inputs , in+ and in?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v . if the analog input signal exceeds this level, the diode s be come forward - bias ed and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4841 in figure 23) are different from those of ref , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short - circuit ) , the cur rent limitation can be used to protect the part. figure 24 . equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. figure 25 . analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor, c pin , an d the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, where the switches are close d, the input impedance is limited to c pin . r in and c in make a 1 - pole, low - pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad7984 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the sour ce impedance and the maximum input frequency. driver amplifier cho ice although the ad7984 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the dr iver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7984 . the noise from the driver is filtered by the ad7984 analog input circuit s 1 - pole, low - pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7984 is 3 6.24 v rms , the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 .24 6 3 36.24 log 20 n 3db loss ne f snr ere f C 3db is the input bandwidth , in megahertz, of the ad7984 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for examp le, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd perfor - mance commensurate with the ad7984 . ? for multichannel multiplexed applications, the driver amplifier and the ad7984 analog input circuit must settle for a full - scale step onto the capacitor array at a n 18- bit level (0.0004%, 4 ppm). in the data sheet of the amplifier , settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a n 18 - bit level and should be verified prior to driver selection. table 8 . recommended driver amplifiers amplifier typical application ada4941 -x very low noise, low power single - to - differential ada4841 -x very low noise, small, and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8655 5 v single supply, low noise ad8605 , ad8615 5 v single supply, low pow er c pin ref r in c in d1 d2 in+ or in? gnd 06973-014 90 85 80 75 70 65 60 1 10 100 1000 10000 frequency (khz) cmrr (db) 06973-015 rev. b | page 14 of 24
data sheet ad7984 single - to - differential driver for applications using a single - ended analog signal, either bipolar or unipolar, the ada4941 - x single - ended - to - differential driver allows for a differential input into the part. the schematic is shown in figure 26. r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2 , and c f are chosen depending on the desired input res istance, signal bandwidth, anti aliasing , an d noise contribution. for example, for the 10 v range with a 4 k? impedance, r2 = 1 k? and r1 = 4 k? . r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc . the common mode should be close to v ref /2. for example, for the 10 v range with a single supply, r3 = 8.45 k?, r4 = 11.8 k? , r5 = 10.5 k?, and r6 = 9.76 k? . figure 26 . single - ended - to- differential driver circuit voltage reference in put the ad7984 voltage refe rence input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source ( for example, a reference buffer using the ad8031 or the ad8605 ) , a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference - decoupling capacitor with va lues as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7984 uses two power supply pins: a core supply ( vdd ) and a digital input/output interface supply ( vio ) . vio allows direct interface with any logic between 1.8 v and 5.5 v . to reduce the number of supplies needed, vio and vdd can be tied together. the ad7984 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range , as shown in figure 27. figure 27 . ps rr vs. frequency 15? 15? 10f r1 100nf +2.5v +5v ref +5.2v ?0.2v c f r2 r4 r6 10v, 5v, .. r3 r5 ref vdd gnd in+ in? ad7984 2.7nf 2.7nf ada4941 in fb outp outn ref 100nf 06973-016 95 90 85 80 75 70 65 60 psrr (db) 1 10 100 1000 frequency (khz) 06973-017 rev. b | page 15 of 24
ad7984 data sheet digital interface alt hough the ad7984 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the ad7984 is compatible with spi, qspi ? , digital hosts, and dsps. in t his mode, the ad7984 can use either a 3 - wire or 4 - wire interface . a 3 - wire interface using the cnv, sck, and sdo signals minimizes wiri ng connections useful, for instance, in isolated applications. a 4 - wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7984 provides a daisy - chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register . the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high , and the chain mode is selected if sdi is low. the sdi hold time is such that when sd i and cnv ar e connected , the chain mode is always selected. in either mode, the ad7984 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled ? in cs mode i f cnv or sdi is low when the adc conversion ends ( see figu re 31 and figure 35). ? in chain mode if sck is high during the cnv rising edge ( see figure 39). rev. b | page 16 of 24
data sheet ad7984 cs mode , 3 - wire without busy indicator this mode is usually used when a single ad7984 is c onnected to an spi - compatible digital host. the connection diagram is shown in figure 28, and the corresponding timing is given in figure 29. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. when a conversion is initiated, it continue s until completion irrespective of the state of cnv. this can be useful, for example , to bring cnv low to select other spi devices, such as analog multiplexers ; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7984 enters the acquisition phase and goes into standby mode . when cnv goes low, the msb is output onto sdo. th e remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate , provided it has an acc eptable hold time. after the 18 th sck falling edge or when cnv goes high ( whichever occurs first) , sdo returns to high impedance. figure 28 . cs mode , 3- wire without busy indicator connection diagram (sdi high) figure 29 . cs mode , 3 - wire without busy indicator serial interface timing (sdi high) ad7984 sdi sdo cnv sck convert data in clk digital host vio 06973-018 sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 16 17 18 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 06973-019 rev. b | page 17 of 24
ad7984 data sheet cs mode , 3 - wire w ith busy indicator this mode is usually used when a single ad7984 is connected to an spi - compatible digital host having an interrupt input. the connection diagram is shown in figure 30, and the corresponding timing is given in figu re 31. with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. pr ior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee th e generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance . with a pull - up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by the d igital host. the ad7984 then enters the acquisition phase and goes into standby mode . the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the d ata, a digital host using the sck falling edge allow s a faster reading rate , provided it has an acceptable hold time. after the optional 19 th s ck falling edge or when cnv goes high ( whichever occurs first) , sdo returns to high impedance. if multiple ad7984 s are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. figure 30 . cs mode , 3- wire w ith busy indicator connection diagram (sdi high) figu re 31 . cs mode , 3- wire w ith busy indicator serial interface timing (sdi high) ad7984 sdi sdo cnv sck convert data in clk digital host vio irq vio 47k? 06973-020 sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq 06973-021 rev. b | page 18 of 24
data sheet ad7984 cs mode , 4 - wire without busy indicator this mode is usually used when multip le ad7984 s are connected to an spi - compatible digital host. a connection diagram example using two ad7984 s is shown in figure 32, and the corresponding timing is given in figure 33. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback ( i f sdi and cnv are low, sdo i s driven low) . prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7984 enters the acquisition phase and goes into standby mode . each adc result can be read by bringing its sdi input low , which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allow s a faster reading rate , provided it has an acceptable hold time. after the 18 th sck falling edge or when sdi goes high ( whichever occurs first) , sdo returns to high impedance and another ad7984 can be read. figure 32 . cs mode , 4- wire without busy indicator connection diagram figure 33 . cs mode , 4- wire without busy indicator serial interface timing ad7984 sdi sdo cnv sck convert data in clk digital host cs1 cs2 ad7984 sdi sdo cnv sck 06973-022 sdo d17 d16 d15 d1 d0 t dis sck 1 2 3 34 35 36 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 sdi(cs2) 06973-023 rev. b | page 19 of 24
ad7984 data sheet cs mode , 4 - wire w ith busy indicator this mode is usually used when a single ad7984 is connected to an spi - compatible digital host with an interrupt input and when it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select t he data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 34, and t he corresponding timing is given in figure 35. with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback . ( if sdi and cnv are low, sdo is driven low . ) prior to the minimum conversion time, sdi can be used to select other sp i devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is comp lete, sdo goes from high impedance to low impedance . with a pull - up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7984 then enters the acquisition phase and goes into standby mode . the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digi tal host using the sck falling edge allow s a faster reading rate , provided it has an acceptable hold time. after the optional 19 th sck falling edge or sdi going high ( whichever occurs first) , sdo returns to high impedance. figure 34 . cs mode , 4- wire w ith busy indicator connection diagram figure 35 . cs mode , 4- wire w ith busy indicator serial interface timing ad7984 sdi sdo cnv sck convert data in clk digital host irq vio 47k? cs1 06973-024 sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 06973-025 rev. b | page 20 of 24
data sheet ad7984 chain mode w ithout busy indicator this mode can be used to daisy - chain multiple ad7984 s on a 3 - wire serial interface. this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7984 s is shown in figure 36, and the corresponding timing is given in figure 37. when sdi and cnv are low, sdo is driven low. wi th sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is outpu t onto sdo and the ad7984 enters the acquisition phase and goes into standby mode . the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for ea ch adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the r ising edge can be used to capture the data, a digital host using the sck falling edge will allow a faster reading rate and consequently more ad7984 s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 36 . chain mode without busy indicator connection diagram figure 37 . chain mode without busy indicator serial interface timing convert data in clk digital host ad7984 sdi sdo cnv b sck ad7984 sdi sdo cnv a sck 06973-026 sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 34 35 36 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 16 17 t sck t sckl t sckh d a 0 19 20 18 sdi a = 0 sdo b d b 17 d b 16 d b 15 d a 1 d b 1 d b 0 d a 17 d a 16 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 06973-027 rev. b | page 21 of 24
ad7984 data sheet chain mode w ith busy indicator this mode can also be used to daisy - chain multiple ad7984 s on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for systems with a limited interfacing capacity. dat a readback is analogous to clocking a shift register. a connection diagram example using three ad7984 s is shown in figure 38, and the corresponding timing is given in figure 39. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have c ompleted their conversions, the sdo pin of the adc closest to the digital host (see the ad7984 adc labeled c in figure 38 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7984 then enters the acquisition phase and goes into standby mode . the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc i n the chain outputs its data msb first, and 18 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge a llows a faster reading rate and , consequently , more ad7984 s in the chain, provided the digital host has an acceptable hold time. figure 38 . chain mode w ith busy indicator connection diagram figure 39 . chain mode w ith busy indicator serial interface timing convert data in clk digital host ad7984 sdi sdo cnv c sck ad7984 sdi sdo cnv a sck irq ad7984 sdi sdo cnv b sck 06973-028 sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 17 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1 d b 0 d a 17 d a 16 55 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1 d a 0 d c 1 d c 0 d a 16 21 35 36 20 37 d b 1 d b 0 d a 17 d b 17 d b 16 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 06973-029 rev. b | page 22 of 24
data sheet ad7984 application hints layout the printed circuit board (pcb) that houses the ad7984 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7984 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7984 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided . at least one ground plane should be used. it can be common or split between the digital and analog section s . in the latter case, the planes should be joined underneath the ad7984 . the ad7984 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and con nect ing them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7984 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7984 and connected using short , wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of layout following these rules is shown in figure 40 and figure 41. evaluating the ad7984 performance other recommended layouts for the ad7984 are outlined in the documentation of the evaluation board for the ad7984 ( e va l - ad7984 sd z ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - sdp - cb1z . figure 40 . example layout of the ad7984 (t op layer) figure 41 . example layout of the ad7984 (bottom layer) ad7984 06973-030 06973-031 rev. b | page 23 of 24
ad7984 data sheet outline dimensions figure 42 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters figure 43 . 10 - lead lead frame chip scale package [ lfcsp_wd ] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 , 2 , 3 temperature range package description package option ordering quantity branding ad7984brmz ?40c to +85c 10 - lead msop rm -10 tube, 50 c60 ad7984brmz -rl7 ?40c to +85c 10 - lead msop rm -10 reel, 1 , 000 c60 ad7984bcpz -rl7 ?40c to +85c 10 - lead lfcsp_wd cp -10 -9 reel, 1 , 5 00 c60 ad7984bcpz -rl ?40c to +85c 10 - lead lfcsp_wd cp -10 -9 reel, 5 , 000 c60 eval - ad7984sd z evaluation board eval - sdp - cb1z evaluation board 1 z = rohs compliant part. 2 the eval - ad7984sdz board can be used as a standalone evaluation board or in conjunction with the eval - sdp - cb1z for evaluation/d emonstration purposes. 3 the eval - sdp - cb1z board allows a pc to control and communicate with all analog devices evaluation boards ending in the sd designator. c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - b a 0 9 1 7 0 9 - a 6 0 0 . 7 0 0 . 5 5 0 . 4 0 5 1 0 1 6 0 . 5 0 b s c 0 . 3 0 0 . 1 5 1 . 1 0 m a x 3 . 1 0 3 . 0 0 2 . 9 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 1 3 3 . 1 0 3 . 0 0 2 . 9 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min ? 2007 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06973 - 0 - 7/14(b) rev. b | page 24 of 24

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